This invention is in the field of multi-processor digital computer systems. In particular, it relates to the synchronization of communication between a plurality of processors.
In the multi-processor environment, various resources can be accessed by each of the processors. For example, input/output devices such as printers and CRTs may be used at different times by each and every processor.
In certain situations, the use of certain resources, if these resources are accessed concurrently by different processors, can result in errors due to data coherency. For example, if a general purpose register is used as a counter and if two different processors read, increment and write the register at the same time, the count in the register will be incorrect.
For resources where utilization by multiple processors can create data coherency problems, some method to synchronize and control access to the resource must be implemented. Although software "Test and Set" flags exist, they are not without drawbacks. In particular, as each setting and testing of the flag requires the processor to obtain busmastership, a great deal of time is spent gaining busmastership for a relatively simple task. This wasted time can add up quickly in a multi-processor environment. A method and apparatus which can coordinate access to resources between the multiple processors in a minimum amount of time and without requiring extensive additional hardware or software is therefore desirable.